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this document is a general product description and is subject to change without notice. hynix do es not assume any responsibilit y for use of circuits described. no patent licenses are implied. rev. 0.2/ nov. 2005 1 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash 8gb nand flash hy27ug088g2m hy27ug088g5m hy27ug088gdm
rev. 0.2 / nov. 2005 2 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash document title 8gbit (1gx8bit) nand flash memory revision history revision no. history draft date remark 0.0 initial draft. sep. 08. 2005 initial 0.1 1) add hy27ug088g5m & hy27ug088gdm products. - texts & figures are added. 2) change ac characteristics 3) add tcrrh (100ns, min) - tcrrh: cache read re# high 4) change 3rd read id - 3rd read id is changed to c1h - 3rd byte of device identifier table is added. 5) change nop - number of partial program cycle in the same page is changed to 4. 6) delete concurrent operation. oct. 23. 2005 preliminary 0.2 1) change ac characteristics nov. 16. 2005 preliminary tr tar trea trhz tchz tcea before 20 10 18 30 30 25 after251520505035 tcls twp tds twc tadl trp trc before 12 12 12 25 70 12 25 after 15 15 15 30 100 15 30 trea tcea tcs before 20 35 20 after 25 30 25
rev. 0.2 / nov. 2005 3 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash features summary high density nand flash memories - cost effective solutions for mass storage applications nand interface - x8 width. - multiplexed address/ data - pinout compatibility for all densities supply voltage - 3.3v device: vcc = 2.7 to 3.6v : hy27ug088g(2/5/d)m memory cell array = (2k+ 64) bytes x 64 pages x 8,192 blocks page size - x8 device : (2k + 64 spare) bytes : hy27ug088g(2/5/d)m block size - x8 device: (128k + 4k spare) bytes page read / program - random access: 25us (max.) - sequential access: 30ns (min.) - page program time: 200us (typ.) copy back program mode - fast page copy without external buffering cache program mode - internal cache register to improve the program throughput fast block erase - block erase time: 2ms (typ.) status register electronic signature - manufacturer code - device code chip enable don't care option - simple interface with microcontroller automatic page 0 read at power-up option - boot from nand support - automatic memory download serial number option hardware data protection - program/erase locked during power transitions data integrity - 100,000 program/erase cycles - 10 years data retention package - hy27ug088g2m-t(p) : 48-pin tsop1 (12 x 20 x 1.2 mm) - hy27ug088g2m-t (lead) - hy27ug088g2m-tp (lead free) - hy27ug088g5m-t(p) : 48-pin tsop1 (12 x 20 x 1.2 mm) - hy27ug088g5m-t (lead) - hy27ug088g5m-tp (lead free) - hy27ug088gdm-up :52- ulga (12 x 17 x 0.65 mm) - hy27ug088gdm-dp (lead free)
rev. 0.2 / nov. 2005 4 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash 1. summary description the hynix hy27ug088g(2/5/d)m series is a 1gx8bit with spare 32mx8 bit capacity. the device is offered in 3.3v vcc power supply. its nand cell provides the most cost-effective solution for the solid state mass storage market. the memory is divided into blocks that can be erased indepe ndently so it is possible to preserve valid data while old data is erased. the device contains 8192 blocks, composed by 64 pages cons isting in two nand structures of 32 series connected flash cells. a program operation allows to write the 2112-byte page in typical 200us and an erase operation can be performed in typical 2ms on a 128k-byte(x8 device) block. data in the page mode can be read out at 30ns cycle time per byte. the i/o pins serve as the ports for address and data input/output as well as command input. this interface allows a reduced pin count and easy migration towards dif- ferent densities, without any rearrangement of footprint. commands, data and addresses are synchronously in troduced using ce#, we#, ale and cle input pin. the on-chip program/erase controller automates all progra m and erase functions including pulse repetition, where required, and internal verifica tion and margining of data. the modifying can be locked using the wp# input pin. the output pin rb# (open drain buffer) signals the status of the device during each operat ion. in a system with mul- tiple memories the rb# pins can be connected al l together to provide a global status signal. even the write-intensive systems can take advantage of the hy27ug088g(2/5/d)m extended reliability of 100k pro- gram/erase cycles by providing ecc (error correc ting code) with real time mapping-out algorithm. optionally the chip could be offered with the ce# don?t care function. this option allows the direct download of the code from the nand flash memory device by a microcontrol ler, since the ce# transitions do not stop the read opera- tion. the copy back function allows the opti mization of defective blocks management: when a page program operation fails the data can be directly programmed in another page inside the same array section withou t the time consuming serial data insertion phase. the cache program feature allows the data insertion in the ca che register while the data register is copied into the flash array. this pipelined program operation improves the program throughput when long files are written inside the memory. a cache read feature is also implemente d. this feature allows to dramatically improve the read throughput when con- secutive pages have to be streamed out. this device includes also extra features like otp/unique id area, block lock mechanism, automatic read at power up, read id2 extension. the hynix hy27ug088g(2/5/d)m series is available in 48 - tsop1 12 x 20 mm, 52-ulga 12 x 17 mm. 1.1 product list part number orization vcc range package hy27ug088g(2/5)m x8 2.7v - 3.6 volt 48tsop1 hy27ug088gdm x8 2.7v - 3.6 volt 52-ulga
rev. 0.2 / nov. 2005 5 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash figure1: logic diagram 9&& 966 35( :3 &/( $/( 5( :( &( ,2a,2 5% io7 - io0 data input / outputs cle command latch enable ale address latch enable ce# chip enable re# read enable we# write enable wp# write protect rb# ready / busy vcc power supply vss ground nc no connection pre power-on read enable, lock unlock table 1: signal names
rev. 0.2 / nov. 2005 6 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash figure 2. 48tsop1 contactions, x8 device 1& 1& 1& 1& 1& 1& 5% 5( &( 1& 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 35( 9ff 9vv 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1$1')odvk 7623 [ figure 3. 48tsop1 contacti ons, x8 device (2ce) 1& 1& 1& 1& 1& 5% 5% 5( &( &( 1& 9ff 9vv 1& 1& &/( $/( :( :3 1& 1& 1& 1& 1& 1& 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 9ff 9vv 1& 1& 1& ,2 ,2 ,2 ,2 1& 1& 1& 1& 1$1')odvk 7623 [
rev. 0.2 / nov. 2005 7 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash 1& 1& 1& 1& 1& 1& :( ,2 ,2 ,2 1& $/( :( :3 966 ,2 ,2 ,2 ,2 ,2 ,2 ,2 ,2 966 ,2 5% 5( :3 ,2 ,2 ,2 ,2 1& 5% 966 966 9&& 9&& 1& &/( $/( &( 5( 1& &/( &( 1& 1& 1& 1& 1& 1& $ % & ' ( ) * + - . / 0 1 figure 4. 52-ulga contactions, x8 device, dual interface (top view through package)
rev. 0.2 / nov. 2005 8 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash 1 .2 pin description pin name description io0-io7 data inputs/outputs the io pins allow to input command, address and data and to output data during read / program operations. the inputs are latched on the rising edge of write enable (we#). the i/o buffer float to high-z when the device is desele cted or the outputs are disabled. cle command latch enable this input activates the latching of the io inputs inside the command register on the rising edge of write enable (we#). ale address latch enable this input activates the latching of the io inputs inside the address register on the rising edge of write enable (we#). ce#/ce#1 chip enable this input controls the selection of the device. when the device is busy ce#/ce#1 low does not deselect the memory. ce#2 chip enable the ce#2 input enable the second hy27ug088g5m we# write enable this input acts as clock to latch command, addres s and data. the io inputs are latched on the rise edge of we#. re# read enable the re# input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid trea after the falling edge of re# which also increments the internal column address counter by one. wp# write protect the wp# pin, when low, provides an hardware prot ection against undesired modify (program / erase) operations. rb#1/rb#2 ready busy the ready/busy output is an open drain pin that signals the state of the memory. vcc supply voltage the vcc supplies the power for all the operations (read, write, erase). vss ground nc no connection pre to enable power on auto read. when pre is a logic high, power on auto read mode is enabled, and when pre is a logic low, power auto read mode is disabled. power on auto read mode is available only on 3.3v device. not using power-on auto-read, co nnect it vss or leave it n.c. table 2: pin description note: 1. a 0.1uf capacitor should be connected between the v cc supply voltage pin and the vss ground pin to decouple the current surges from the power supply. the pcb trac k widths must be sufficient to carry the currents required during program and erase operations.
rev. 0.2 / nov. 2005 9 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash io0 io1 io2 io3 io4 io5 io6 io7 1st cycle a0 a1 a2 a3 a4 a5 a6 a7 2nd cycle a8 a9 a10 a11 l (1) l (1) l (1) l (1) 3rd cycle a12 a13 a14 a15 a16 a17 a18 a19 4th cycle a20 a21 a22 a23 a24 a25 a26 a27 5th cycle a28 a29 a30 l (1) l (1) l (1) l (1) l (1) table 3: addre ss cycle map(x8) note: 1. l must be set to low. table 4: address cycle map(2ce & dual) note: 1. l must be set to low. function 1st cycle 2nd cycle 3rd cycle acceptable command during busy read 1 00h 30h - read for copy-back 00h 35h - read id 90h - - reset ffh - - yes page program (start) 80h 10h - copy back pgm (start) 85h 10h - cache program 80h 15h - block erase 60h d0h - read status register 70h - - yes random data input 85h - - random data output 05h e0h - cache read start 00h 31h - cache read exit 34h - - lock block 2ah - - lock tight 2ch - - unlock (start area) 23h - - unlock (end area) 24h - - read lock status 7ah - - table 5: command set io0 io1 io2 io3 io4 io5 io6 io7 1st cycle a0 a1 a2 a3 a4 a5 a6 a7 2nd cycle a8 a9 a10 a11 l (1) l (1) l (1) l (1) 3rd cycle a12 a13 a14 a15 a16 a17 a18 a19 4th cycle a20 a21 a22 a23 a24 a25 a26 a27 5th cycle a28 a29 l (1) l (1) l (1) l (1) l (1) l (1)
rev. 0.2 / nov. 2005 10 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash cle ale ce# we# re# wp# mode h l l rising h x read mode command input l h l rising h x address input(5 cycles) h l l rising h h write mode command input l h l rising h h address input(5 cycles) lllrisinghhdata input ll l (1) h falling x sequential read and data output l l l h h x during read (busy) xxxxxhduring program (busy) xxxxxhduring erase (busy) xxxxxlwrite protect xxhxx0v/vccstand by table 6: mode selection note: 1. with the ce# don?t care option ce# high during latency time does not stop the read operation
rev. 0.2 / nov. 2005 11 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash 2. bus operation there are six standard bus operations that control the devi ce. these are command input, address input, data input, data output, write protect, and standby. typically glitches less than 5 ns on chip enable, write enable and read enable are ignored by the memory and do not affect bus operations. 2.1 command input. command input bus operation is used to give a command to the memory device. command are accepted with chip enable low, command latch enable high, address latch enable low and read enable high and latched on the rising edge of write enable. moreover for commands that starts a modifying operation (write/erase) the write protect pin must be high. see figure 6 and table 14 for details of the timings requirements. command codes are always applied on io7:0, disregarding the bus configuration (x8). 2.2 address input. address input bus operation allows the insertio n of the memory address. to insert the 30 (1) addresses needed to access the 8gbit 5 clock cycles are needed. addresses are acce pted with chip enable low, address latch enable high, command latch enable low and read enable high and latche d on the rising edge of write enable. moreover for com- mands that starts a modify operation (write/erase) the writ e protect pin must be high. see figure 7 and table 14 for details of the timings requirements. addresses are always ap plied on io7:0, disregarding the bus configuration (x8). 2.3 data input. data input bus operation allows to feed to the device the data to be programm ed. the data insertion is serially and timed by the write enable cycles. data are accepted only wi th chip enable low, addre ss latch enable low, command latch enable low, read enable high, and write protect high and latched on the rising edge of write enable. see figure 8 and table 14 for details of the timings requirements. 2.4 data output. data output bus operation allows to read data from the me mory array and to check the st atus register content, the lock status and the id data. data can be serially shifted ou t toggling the read enable pin with chip enable low, write enable high, address latch enable low, and command latc h enable low. see figures 9,11,12 and table 14 for details of the timings requirements. 2.5 write protect. hardware write protection is activated when the write protec t pin is low. in this condition modify operation do not start and the content of the memory is not altered. write pr otect pin is not latched by wr ite enable to ensure the pro- tection even during the power up. 2.6 standby. in standby mode the device is deselected, output s are disabled and power consumption is reduced. note: 1. 29 addresses are needed to access hy27ug088g5m & hy27ug088gdm.
rev. 0.2 / nov. 2005 12 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash 3. device operation 3.1 page read. upon initial device power up, the device defaults to read mode. this operation is also initiated by writing 00h and 30h to the command register along with five address cycles. in two consecutive read operatio ns, the second one doesn?t? need 00h command, which five address cycles and 30h command initiates that operation. two types of operations are available : random read, serial page read. the random read mode is enabled when the page address is changed. the 2112 bytes (x8 device) of data within the selected page are transferred to the data registers in less than 25us(tr). the system controller may detect the completion of this data tr ansfer (tr) by analyzing the output of r/b pin. once the data in a page is loaded into the data registers, they may be read out in 30ns cycle time by sequ entially pulsing re#. the repetitive high to low transitions of the re# clock make the device output th e data starting from the selected col- umn address up to the last column address. the device may output random data in a page instead of th e consecutive sequential data by writing random data out- put command. the column address of next data, which is going to be out, may be changed to the address which follows random data output command. random data output can be operated multiple times re gardless of how many times it is done in a page. 3.2 page program. the device is programmed basically by page, but it does allo w multiple partial page programming of a word or consec- utive bytes up to 2112 (x8 device) , in a single page prog ram cycle. the number of cons ecutive partial page program- ming operation within the same page wi thout an intervening erase operation must not exceed 4 times for main array (x8 device:1time/512byte) and 4 times fo r spare array (x8 device:1time/16byte). the addressing should be done in sequential order in a block 1 . a page program cycle consists of a serial data loading period in which up to 2112bytes (x8 device) or 1056wo rds (x16 device) of data may be loaded into the data register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell. the serial data loading period begins by inputting the serial data input comma nd (80h), followed by the five cycle address inputs and then serial data. the words other than those to be programmed do not need to be loaded. the device supports random data input in a page. the column address of next data, which will be entered, may be changed to the address which follows random data input co mmand (85h). random data input may be operated multi- ple times regardless of how many times it is done in a page. the page program confirm command (10h) initiates the prog ramming process. writing 10h alone without previously entering the serial data will not initia te the programming process. the internal write state controller automatically exe- cutes the algorithms and timings necessary for program and verify, thereby freeing the system controller for other tasks. once the program process starts, the read status regi ster command may be entered to read the status register. the system controller can detect the completion of a progra m cycle by monitoring the rb# output, or the status bit (i/ o 6) of the status register. only the read status command and reset command are valid while programming is in progress. when the page program is complete, the write status bit (i/o 0) may be checked. the internal write verify detects only errors for "1"s that are not successfully prog rammed to "0"s. the command register remains in read sta- tus command mode until another valid co mmand is written to the command register. figure 14 details the sequence.
rev. 0.2 / nov. 2005 13 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash 3.3 block erase. the erase operation is done on a block basis. block address loading is accompli shed in three cycles initiated by an erase setup command (60h). only address a18 to a30 (1) (x8) is valid while a12 to a17 (x8) is ignored. the erase con- firm command (d0h) following the block address loading initia tes the internal erasing proce ss. this two-step sequence of setup followed by execution command ensures that memory contents are not accidental ly erased due to external noise conditions. at the rising edge of we# after the erase confirm command input, the internal write controller handles erase and erase-verify. once the erase process starts, the read status register co mmand may be entered to read the status register. the sys- tem controller can detect the completion of an erase by mo nitoring the rb# output, or the status bit (i/o 6) of the status register. only the read status command and reset command are valid while erasing is in progress. when the erase operation is completed, the write status bit (i/o 0) may be checked. figure 19 details the sequence. 3.4 copy-back program. the copy-back program is configured to quickly and efficien tly rewrite data stored in on e page without utilizing an external memory. since the time-consuming cycles of serial access and re-loading cycles are removed, the system per- formance is improved. the bene fit is especially obvious when a portion of a block is updated and the rest of the block also need to be copied to the newl y assigned free block. the operation for performing a copy-back program is a sequential execution of page-read with out serial access and copying-program with the address of destination page. a read operation with "35h" command and the address of th e source page moves the whole 2112byte (x8 device) data into the internal data buffer. as soon as the device returns to ready state, co py back command (85h) with the address cycles of destination page may be written. the program co nfirm command (10h) is required to actually begin the pro- gramming operation. data input cycle for modifying a portion or multiple distant po rtions of the source page is allowed as shown in figure 16. "when there is a program-failure at copy-back operatio n, error is reported by pass/fail status. but, if copy-back operations are accumulated over time, bit error due to charge loss is not checked by external error detection/correction scheme. for this reason, two bit error correction is recommended for the use of copy-back operation." figure 16 shows the command sequ ence for the copy-back operation. the copy back program operation requires three steps: 1. the source page must be read using the read a co mmand (one bus write cycle to setup the command and then 5 bus write cycles to input the source page address). th is operation copies all 2kbytes from the page into the page buffer. 2. when the device returns to the re ady state (ready/busy high), the seco nd bus write cycle of the command is given with the 5bus cycles to input th e target page address. the value for a29, a30 (2) from second to the last page address must be same as the value given to a29, a30 (2) in first address. 3. then the confirm command is issu ed to start the p/e/r controller. note: 1. 29 addresses are needed to access hy27ug088g5m & hy27ug088gdm. 2. a30 is not needed. (hy27ug088g5m & hy27ug088gdm)
rev. 0.2 / nov. 2005 14 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash 3.5 read status register. the device contains a status register which may be read to find out whether read, program or erase operation is com- pleted, and whether the program or eras e operation is completed successfully. after writing 70h command to the com- mand register, a read cycle outputs the co ntent of the status register to the i/ o pins on the falling edge of ce# or re#, whichever occurs last. this two line control allows the system to poll th e progress of each device in multiple memory connections even when rb# pins are common-wired. re# or ce# does not need to be toggled for updated status. refer to table 15 for specific status register defi nitions. the command register remains in status read mode until further commands are issued to it. th erefore, if the status register is read during a random read cycle, the read command (00h) should be given before starting read cycles. see figure 13 for details of the read status operation. 3.6 read id. the device contains a product identification mode, initiate d by writing 90h to the command register, followed by an address input of 00h. four read cycles sequentially output the manufacturer co de (adh), and the device code and 3rd cycle id, 4th cycle id, respectively. the command register re mains in read id mode until further commands are issued to it. figure 21 shows the operation sequence, while tables 16 to 19 explain the byte meaning. 3.7 reset. the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during random read, program or erase mode, the reset operat ion will abort these operatio ns. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. the command register is cleared to wait for the next command, and the status regist er is cleared to value e0h when wp# is high. refer to table 15 for device status after reset oper ation. if the device is already in reset state a new reset command will not be accepted by the command register. the rb# pin transitions to low for trst after the reset command is written. refer to figure 30.
rev. 0.2 / nov. 2005 15 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash 3.8 cache program. cache program is an extension of page program, which is executed with 2112byte (x8 device) data registers, and is available only within a block. since the device has 1 page of cache memory, serial data input may be executed while data stored in data register are programmed into memory ce ll. after writing the first set of data up to 2112byte (x8 device) or 1056word (x16 device) into the selected cache re gisters, cache program command (15h) instead of actual page program (10h) is input to make cache registers free an d to start internal program op eration. to transfer data from cache registers to data registers, the device remains in busy state for a short period of time (tcbsy) and has its cache registers ready for the next data-input while the inte rnal programming gets started with the data loaded into data registers. read status command (70h) may be issued to find out when cache regist ers become ready by polling the cache-busy status bit (i/o 6). pass/fail status of only the previous page is availa ble upon the return to ready state. when the next set of data is input with the cache program command, tc bsy is affected by the progress of pending internal programming. the programming of the cach e registers is initiated only when the pending program cycle is finished and the data registers ar e available for the transfer of data from cache registers. the status bit (i/o5) for internal ready/busy may be polled to iden tify the completion of internal programming. if the system monitors the progress of programming only wi th rb#, the last page of th e target programming sequence must be programmed with actual page program command (10h). if the cache program command (15h) is used instead, status bit (i/o5) must be polled to find out when the last programming is actually finished before starting other operations such as read. pass/fail status is available in two steps. i/o 1 returns with the status of the previous page upon ready or i/o6 status bit chan ging to "1", and later i/o 0 with the st atus of current page upon true ready (returning from internal programming) or i/o 5 status bit ch anging to "1". i/o 1 may be read together when i/o 0 is checked. see figure 17 for more details. note : since programming the last page does not employ caching, the program time has to be that of page program. however, if the previous program cycle with the cache data has not finished, the actual program cycle of the last page is initiated only after completi on of the previous cycle, which can be expressed as the following formula. tprog= program time for the last page+ program time for the ( last -1 )th page - (program command cycle time + last page data loading time) the value for a29, a30 (1) from second to the last page address must be same as the value given to a29, a30 (1) in first address. note: 1. a30 is not needed. hy27088g5m & hy27088gdm
rev. 0.2 / nov. 2005 16 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash 3.9 cache read cache read operation allows automatic download of consecut ive pages, up to the whole device. immediately after 1st latency end, while user can start reading out data, device internally starts reading following page. start address of 1st page is at page start (a<10:0>=00h), af ter 1st latency time (tr) , automatic data download will be uninterrupted. in fact latency time is 25us, while download of a page require at least 100us for x8 device. cache read operation command is like standard read, except for confirm code (30h for standard read, 31h for cache read) user can check operation status using : - rb# ( ?0? means latency ongoing, download not possible, ?1? means download of n page possible, even if device internally is active on n+1 page - status register (sr<6> behave like rb#, sr<5> is ?0? when device is internally reading and ?1? when device is idle) to exit cache read operation a cache read exit command ( 34h) must be issued. this command can be given any time (both device idle and reading). if device is active (sr<5>=0) it will go idle within 5us, whil e if it is not active, device itself will go busy for a time shorter then trbsy before becoming again idle and ready to accept any further commands. if user arrives reading last byte/word of the memory array, then has to stop by giving a cache read exit command. random data output is not available in cache read. cache read operation must be done only block by block if system needs to avoid reading also from invalid blocks.
rev. 0.2 / nov. 2005 17 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash 4. other features 4.1 data protection & power on/off sequence the device is designed to offer protection from any involu ntary program/erase during powe r-transitions. an internal voltage detector disables all functions whenever vcc is below about 2v(3.3v device). wp# pin provides hardware pro- tection and is recommended to be kept at vil during power-up an d power-down. a recovery time of minimum 10us is required before internal circuit gets ready for any command sequences as shown in figure 33. the two-step command sequence for program/erase provides additional software protection. 4.2 ready/busy. the device has a ready/busy output that provides method of indicating the co mpletion of a page program, erase, copy-back, cache program and random read completion. th e rb# pin is normally high and goes to low when the device is busy (after a reset, read, program, erase operatio n). it returns to high when th e internal controller has fin- ished the operation. the pin is an open-d rain driver thereby allowing two or mo re rb# outputs to be or-tied. because pull-up resistor value is related to tr(r b#) and current drain during busy (ibusy), an appropriate value can be obtained with the following reference chart (fig 32). its va lue can be determined by the following guidance. 4.3 lock block feature in high state of pre pin, block lock mode is enable d, otherwise it is regard ed as nand flash without pre pin. block lock mode is enabled while pre pin state is high, which is to offer protec tion features for nand flash data. the block lock mode is divided into unlock , lock, lock-tight operation. consecutive blocks protects data allows those blocks to be locked or lock-tighten with no latency. this block lock scheme offers two levels of protection. the first allows software control (command input method) of block locking that is useful for frequently changed data blocks, while the second requires hardware control (wp# low pulse input method) before locking can be changed that is use- ful for protecting infrequently changed code blocks . the followings summarized the locking functionality. - all blocks are in a locked state on power-up . unlock sequence can unlock the locked blocks. - the lock-tight command locks blocks and prevents from being unlocked. lock-tight stat e can be returned to lock state only by hardware control(wp low pulse input). 1. block lock operation 1) lock - command sequence: lock bloc k command (2ah). see fig. 24. - all blocks default to locked by power-up and hardware control (wp# low pulse input) - partial block lock is not available; lock block operation is based on all block unit - unlocked blocks can be locked by using the lock block command, and a lo ck block?s status can be changed to unlock or lock-tight using the appropriate commands - on the program or erase operation in locked or lock-tighten block, busy state holds 5~10us(tlbsy)
rev. 0.2 / nov. 2005 18 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash 2) unlock - command sequence: unlock block command (23h) + star t block address + command (24h) + end block address. see fig. 26. - unlocked blocks can be programmed or erased. - an unlocked block?s status can be changed to the locked or lock-tighten state using the appropriate sequence of commands. - only one consecutive area can be released to unlock st ate from lock state; unlockin g multi area is not available. - start block address must be nearer to the logica l lsb (least significant bit) than end block address. - one block is selected for unlocking block when start block address is same as end block address. 3) lock-tight - command sequence: lock-tight bl ock command (2ch). see fig. 27. - lock-tighten blocks offer the user an additional level of wr ite protection beyond that of a regular lock block. a block that is lock-tighten can?t have its state changed by software control, only by hardware control (wp# low pulse input); unlocking multi area is not available - only locked blocks can be lo ck-tighten by lock-tight command. - on the program or erase operation in locked or lock-tighten block, busy state holds 5~10us(tlbsy) 2. block lock status read block lock status can be read on a block basis to find ou t whether designated block is available to be programmed or erased. after writing 7ah command to the command register and block address to be chec ked, a read cycle outputs the content of the block lock status regi ster to the i/o pins on the falling edge of ce# or re#, whichever occurs last. re# or ce# does not need to be toggled for updated status. block lock status read is prohibited while the device is busy state. refer to table 20 for specific status register definitions. the command regist er remains in block lock status read mode until further commands are issued to it. in high state of lockpre pin, write protection stat us can be checked by bloc k lock status read (7ah) while in low state by status read (70h). 4.4 power-on auto-read the device is designed to offer automa tic reading of the first page without command and address input sequence dur- ing power-on. an internal voltage detector enables auto-page read functi ons when vcc reaches about 1.8v. auto-page read function is enabled only when vcc pin is logic high state. se rial access may be done after power-on without latency. power-on auto read mode is available only on 3.3v device.
rev. 0.2 / nov. 2005 19 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash parameter symbol min typ max unit valid block number n vb 8032 8092 blocks table 8: valid blocks number
rev. 0.2 / nov. 2005 20 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash symbol parameter value unit 3.3v t a ambient operating temperature (commercial temperature range) 0 to 70 ambient operating temperature (extended temperature range) -25 to 85 ambient operating temperature (industry temperature range) -40 to 85 t bias temperature under bias -50 to 125 t stg storage temperature -65 to 150 v io (2) input or output voltage -0.6 to 4.6 v vcc supply voltage -0.6 to 4.6 v table 9: absolute maximum ratings note: 1. except for the rating ?operating temperature rang e?, stresses above those listed in the table ?absolute maximum ratings? may cause permanent damage to th e device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sectio ns of this specification is not implied. exposure to absolute maximum rating cond itions for extended periods may affect device reliability. 2. minimum voltage may undershoot to -2v during tran sition and for less than 20ns during transitions.
rev. 0.2 / nov. 2005 21 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash $''5(66 5(*,67(5 &2817(5 352*5$0 (5$6( &21752//(5 +9*(1(5$7,21 &200$1' ,17(5)$&( /2*,& &200$1' 5(*,67(5 '$7$ 5(*,67(5 ,2 5( %8))(56 <'(&2'(5 3$*(%8))(5 ; ' ( & 2 ' ( 5 0elw0elw 1$1')odvk 0(025<$55$< :3 &( :( &/( $/( 35( $a$ figure 5: block diagram
rev. 0.2 / nov. 2005 22 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash parameter symbol test conditions 3.3volt unit min typ max operating current sequential read i cc1 t rc =30ns ce#=v il , i out =0ma -2545ma program i cc2 - - 25 45 ma erase i cc3 - - 25 45 ma stand-by current (ttl) i cc4 ce#=v ih , wp#=pre=0v/vcc -1ma stand-by current (cmos) i cc5 ce#=vcc-0.2, wp#=pre=0v/vcc -20100ua input leakage current i li v in= 0 to vcc (max) single & 2ce - - 20 ua dual - - 10 ua output leakage current i lo v out =0 to vcc (max) single & 2ce - - 20 ua dual - - 10 ua input high voltage v ih - vccx0.8 - vcc+0.3 v input low voltage v il - -0.3 - vccx0.2 v output high voltage level v oh i oh =-400ua 2.4 - - v output low voltage level v ol i ol =2.1ma - - 0.4 v output low current (rb#) i ol (rb#) v ol =0.4v 8 10 - ma table 10: dc and operating characteristics parameter value 3.3volt input pulse levels 0v to vcc input rise and fall times 5ns input and output timing levels vcc/2 output load (2.7v - 3.3v) 1 ttl gate and cl=50pf output load (3.0 - 3.6v) 1 ttlgate and cl=100pf table 11: ac conditions
rev. 0.2 / nov. 2005 23 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash item symbol test condition min max unit input / output capacitance c i/o v il =0v - 20 pf input capacitance c in v in =0v - 20 pf table 12: pin capacita nce (ta=25c, f=1.0mhz) parameter symbol min typ max unit program time t prog - 200 700 us dummy busy time for cache program t cbsy -3700us dummy busy time for cache read t rbsy -5-us dummy busy time for the lock or lock-tight block t lbsy -510us number of partial program cycles in the same page nop - - 4 cycles block erase time t bers -23ms table 13: program / erase characteristics
rev. 0.2 / nov. 2005 24 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash parameter symbol 3.3volt unit min max cle setup time tcls 15 ns cle hold time tclh 5 ns ce# setup time tcs 25 ns ce# hold time tch 5 ns we# pulse width twp 15 ns ale setup time tals 15 ns ale hold time talh 5 ns data setup time tds 15 ns data hold time tdh 5 ns write cycle time twc 30 ns we# high hold time twh 10 ns ale to data loading time tadl (2) 100 ns data transfer from cell to register tr 25 us ale to re# delay tar 15 ns cle to re# delay tclr 15 ns ready to re# low trr 20 ns re# pulse width trp 15 ns we# high to busy twb 100 ns read cycle time trc 30 ns re# access time trea 25 ns re# high to output high z trhz 50 ns ce# high to output high z tchz 50 ns cache read re# high tcrrh 100 ns re# high to output hold trhoh 15 ns re# low to output hold trloh 5 ns ce# high to output hold tcoh 15 ns re# high hold time treh 10 ns output high z to re# low tir 0 ns ce# access time tcea 30 ns we# high to re# low twhr 60 ns device resetting time (read / program / copy-back program / erase) trst 5/10/40/500 (1) us write protection time tww (3) 100 ns table 14: ac timing characteristics note: 1. if reset command (ffh) is written at ready st ate, the device goes into busy for maximum 5us 2. tadl is the time from the we# risi ng edge of final address cycle to the we# rising edge of first data cycle. 3. program / erase enable operation : twp# high to twe# high. program / erase disable operation : twp# low to twe# high.
rev. 0.2 / nov. 2005 25 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash io page program block erase cache program read cache read coding 0 pass / fail pass / fail pass / fail (n) na pass: ?0? fail: ?1? 1na napass / fail (n-1)na pass: ?0? fail: ?1? (only for cache program, else don?t care) 2na na na na - 3na na na na - 4na na na na - 5 ready/busy ready/busy p/e/r controller bit ready/busy p/e/r controller bit active: ?0? idle: ?1? 6 ready/busy ready/busy cache register free ready/busy ready/busy busy: ?0? ready?: ?1? 7 write protect write protect write protect write protect protected: ?0? not protected: ?1? table 15: status register coding device identifier byte description 1st manufacturer code 2nd device identifier 3rd internal chip number, cell type, number of simultaneously programmed pages. 4th page size, block size, spare size, organization table 16: device identifier coding part number voltage bus width manufacture code device code 3rd code 4th code hy27ug088g2m 3.3v x8 adh d3h c1h 95h hy27ug088g5m 3.3v x8 adh dch 80h 95h hy27ug088gdm 3.3v x8 adh dch 80h 95h table 17: read id data table
rev. 0.2 / nov. 2005 26 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash description io7 io6 io5 io4 io3 io2 io1 io0 internal chip number 1 2 4 8 0 0 0 1 1 0 1 1 cell type 2 level cell 4 level cell 8 level cell 16 level cell 0 0 0 1 1 0 1 1 number of simultaneously programmed pages 1 2 4 8 0 0 0 1 1 0 1 1 interleave program between multiple chips not support support 0 1 cache program not support support 0 1 table 18: 3rd byte of device idendifier description description io7 io6 io5-4 io3 io2 io1-0 page size (without spare area) 1k 2k reserved reserved 0 0 0 1 1 0 1 1 spare area size (byte / 512byte) 8 16 0 1 serial access time 50ns/30ns 25ns reserved reserved 0 1 0 1 0 0 1 1 block size (without spare area) 64k 128k 256k reserved 0 0 0 1 1 0 1 1 organization x8 x16 0 1 table 19: 4th byte of device identifier description
rev. 0.2 / nov. 2005 27 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash ,2a,2 ,28qorfn ,2/rfn ,2/rfnwljkw ; ; ; ; 5hdgeorfnfdvh 5hdgeorfnfdvh 5hdgeorfnfdvh 5hdgeorfnfdvh /rfn 8qorfn /rfn /rfnwljkw 8qorfn /rfnwljkw /rfn 8qorfn /rfnwljkw figure 6: command latch cycle w&/ 6 w&6 w:3 &rppdqg &/( &( :( $/( ,2[ w'+ w'6 w$/6 w$/+ w&/+ w&+ table 20: lock status code
rev. 0.2 / nov. 2005 28 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash w&/6 w&6 w:3 w:& w:& w:& w:3 w:3 w:3 w$/6 w:+ w:+ w:+ w:+ w$/+ w$/6 w$/6 w$/6 w$/6 &ro$gg w$/+ w$/+ w$/+ w$/+ w'+ &ro$gg 5rz$gg 5rz$gg 5rz$gg w:& w'+ w'+ w'+ w'+ w'6 w'6 w'6 w'6 w'6 &/( &( :( $/( ,2[ figure 7: address latch cycle figure 8. input data latch cycle w:& w$/6 w&/+ w&+ w:3 w:+ ',1 ',1 ',1ilqdo w'+ w'+ w'+ w'6 w'6 w'6 w:3 w:3 &/( $/( &( ,2[ :( 1rwhv ',1ilqdophdqv
rev. 0.2 / nov. 2005 29 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash figure 9: sequential out cycle after read (cle=l, we#=h, ale=l) w5& &( 5( ,2[ 5% w5($ w55 'rxw 'rxw 'rxw 1rwhv7udqvlwlrqlvphdvxuhgp9iurpvwhdg\vwdwhyrowdj hzlwkordg 7klvsdudphwhulvvdpsohgdqgqrwwhvwhgw&+= w5+= w5/2+lvydolgzkhqiuhtxhqf\lvkljkhuwkdq0+] w5+2+vwduwvwrehydolgzkhqiuhtxhqf\lvorzhuwkdq 0+] w5($ w5+= w5+= w5($ w&+= w&2+ w5+2+ w5(+ w5& w53 w5(+ w5($ w&($ w5/2+ w55 w5($ w&+= w&2+ w5+= w5+2+ 'rxw 'rxw &( 5( ,2[ 5% 1rwhv7udqvlwlrqlvphdvxuhgp9iurpvwhdg\vwdwhyrowdj hzlwkordg 7klvsdudphwhulvvdpsohgdqgqrwwhvwhgw&+= w5+= w5/2+lvydolgzkhqiuhtxhqf\lvkljkhuwkdq0+] w5+2+vwduwvwrehydolgzkhqiuhtxhqf\lvorzhuwkdq 0+] figure 10: sequential out cycle after read (edo type cle=l, we#=h, ale=l)
rev. 0.2 / nov. 2005 30 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash figure 11: status read cycle w &/6 w &/5 w &/+ w &6 w &+ w :3 w :+5 w &($ w '6 w 5($ w &+= w &2+ w 5+= w 5+2+ kru%k 6wdwxv2xwsxw w '+ w ,5 &( :( ,2 [ &/( 5( &/( $/( &( ,2[ :( 5( 5% w :& w &/5 w 55 k k &ro$gg &roxpq$gguhvv 5rz$gguhvv &ro$gg 5rz$gg 5rz$gg %xv\ 'rxw1 'rxw1 'rxw0 w :% w $5 w 5 w 5& w 5+= 5rz$gg figure 12: read1 operation (read one page)
rev. 0.2 / nov. 2005 31 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash w:% w$5 w&+= w&2+ w5& w5 w55 %xv\ k k 'rxw 1 'rxw 1 'rxw 1 &ro $gg &ro $gg 5rz $gg 5rz $gg 5rz $gg &roxpq$gguhvv 5rz$gguhvv &/( &( :( $/( 5( ,2[ 5% figure 13: read1 operation intercepted by ce#
rev. 0.2 / nov. 2005 32 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash &/( $/( &( 5( 5% ,2[ :( w&/5 k &roxpq$gguhvv 5rz$gguhvv %xv\ k k (k 'rxw1 'rxw0 'rxw1 'rxw0 &ro$gg 5rz$gg 5rz$gg 5rz$gg &ro$gg &roxpq$gguhvv &ro$gg &ro$gg w5 w5& w:% w$5 w55 w:+5 w5($ w5+: figure 14 : random data output
rev. 0.2 / nov. 2005 33 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash figure 15: page program operation &/( $/( &( 5( 5% ,2[ :( w:& k &ro $gg 6huldo'dwd ,qsxw&rppdqg &roxpq$gguhvv 5rz$gguhvv 5hdg6wdwxv &rppdqg 3urjudp &rppdqg ,2r 6xffhvvixo3urjudp ,2r (uurulq3urjudp xswrp%\wh 6huldo,qsxw &ro $gg 5rz $gg 5rz $gg 5rz $gg 'lq 1 'lq 0 k k ,2r w:& w:% w352* w:& w$'/
rev. 0.2 / nov. 2005 34 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash &/( $/( &( 5( 5% ,2[ :( w:& k 'lq 1 'lq 0 'lq - 'lq . k k k ,2 &ro$gg &ro$gg &ro$gg &ro$gg 5zr$gg 5zr$gg 5zr$gg w:& w:% w352* 6huldo'dwd ,qsxw&rppdqg 5dqgrp'dwd ,qsxw&rppdqg &roxpq$gguhvv &roxpq$gguhvv 5rz$gguhvv 6huldo,qsxw 6huldo,qsxw 3urjudp &rppdqg 5hdg6wdwxv &rppdqg w:& w$'/ w$'/ figure 16 : random data in
rev. 0.2 / nov. 2005 35 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash %xv\ w:% w:% w$'/ w352* w:& &/( &( :( 5( ,2[ 5% $/( &roxpq$gguhvv k k k 'dwd 'dwd1 k ,2[ %kk &ro $gg &ro $gg 5rz $gg 5rz $gg 5rz $gg &ro $gg &ro $gg 5rz $gg 5rz $gg 5rz $gg 5rz$gguhvv &roxpq$gguhvv 5rz$gguhvv w5 %xv\ &rs\%dfn'dwd ,qsxw&rppdqg figure 17 : copy back program
rev. 0.2 / nov. 2005 36 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash k $gg $gg $gg $gg $gg k ' ' ' ' ' ' ' ' w&55+ 5hdgvwsdjh 5hdgqgsdjh ' ' &/( $/( ,2; 5% 5( :( figure 18: cache read re# high
rev. 0.2 / nov. 2005 37 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash &/( $/( &( 5( 5% ,2[ :( 5% ,2[ ([&dfkh3urjudp w:& k k ,2 3urjudp&rqilup &rppdqg7uxh /dvw3djh,qsxw 3urjudp 0d[wlphvuhshdwdeoh w&%6<pd[xv w&%6< &ro$gg 5rz$gg'dwd w&%6< w&%6< w352* 6huldo'dwd &roxpq$gguhvv 5rz$gguhvv 6huldo,qsxw 3urjudp &rppdqg 'xpp\ k k $gguhvv 'dwd,qsxw $gguhvv 'dwd,qsxw $gguhvv 'dwd,qsxw $gguhvv 'dwd,qsxw k k k k k k k k k 'lq 1 'lq 0 'lq 1 'lq 0 &ro$gg &ro$gg 5rz$gg 5rz$gg &ro$gg &ro$gg 5rz$gg 5rz$gg w:% w352* w:% w&%6< figure 19 : cache program
rev. 0.2 / nov. 2005 38 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash w:& &/( &( :( $/( 5( ,2 [ 5% w:% w%(56 %86< k ,2 'k 5rz $gg 5rz $gg 5rz $gg k $xwr%orfn(udvh 6hwxs&rppdqg (udvh&rppdqg 5hdg6wdwxv &rppdqg ,2 6xffhvvixo(udvh ,2 (uurulq(udvh 5rz$gguhvv figure 20: block erase op eration (erase one block) k &/( &( :( $/( 5( ,2[ k w5($ 5hdg,'&rppdqg $gguhvvf\foh 0dnhu&rgh 'hylfh&rgh $'k wk&\foh ug&\foh 'k &k k w$5 figure 21: read id operation
rev. 0.2 / nov. 2005 39 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash 'k ' 5hdgvwsdjh 5hdgqgsdjh 5hdgugsdjh 5hdgwksdjh ,goh ,goh ' ' ' ' ' ' ' ' ' ' ' ' $gg $gg $gg $gg $gg k ?v ?v ?v ?v ?v ?v ?v &/( $/( :( 5( ,qwhuqdorshudwlrq 6wdwxv5hjlvwhu 65! figure 22: start address at page start :a fter 1st latency uninterrupted data flow ' ,goh ,goh ?vw 5%6< qsdjh qsdjh 5hdgqsdjh ' ' k ' ' ' ' &/( $/( :( 5( 5% ,qwhuqdo rshudwlrq 6wdwxv5hjlvwhu 65! 8vhufdq khuhilqlvk uhdglqj1 sdjh 1sdjh fdqqrweh uhdg ?v ?v ,qwhuuxswhg 5hdg qsdjh figure 23: exit from cache read in 5u s when device internally is reading
rev. 0.2 / nov. 2005 40 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash system interface using ce don?t care t o simplify system interface, ce may be deasserted during data loading or sequential data-reading as shown below. so, it is possible to connect nand flash to a microporcess or. the only function that was removed from standard nand flash to make ce don?t care read operation was disabling of the automatic sequential read function. &(grq?wfduh k 6wduw$gg&\foh 'dwd,qsxw k 'dwd,qsxw &/( &( :( $/( ,2[ figure 24: program operation with ce don?t-care. ,ivhtxhqwldourzuhdghqdeohg &(pxvwehkhogorzgxulqjw5 &(grq?wfduh k k &/( &( 5( $/( 5% :( ,2[ 6wduw$gg&\foh 'dwd2xwsxwvhtxhqwldo w5 figure 25: read operation with ce don?t-care.
rev. 0.2 / nov. 2005 41 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash figure 26: lock command :3 &/( &( :( $/( ,2[ k 8qrfn&rppdqg 6wduw%orfn$gguhvvf\fohv 8qorfn&rppdqg (qg%orfn $gguhvvf\fohv k $gg $gg $gg $gg $gg $gg figure 27: unlock command sequence $k /rfn&rppdqg :3 &/( &( :( ,2[
rev. 0.2 / nov. 2005 42 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash figure 28: lock tight command :3 &/( $/( &( :( ,2[ 5( $k $gg $gg $gg 'rxw 5hdg%orfn/rfn vwdwxv&rppdqg %orfn$gguhvvf\foh w:+5 %orfn/rfn6wdwxv figure 29: lock st atus read timing :3 &/( &( :( ,2[ &k /rfnwljkw&rppdqg
rev. 0.2 / nov. 2005 43 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash 9 9ff :( &( $/( &/( 5% 35( w5 5( ,2[ 'dwd 'dwd 'dwd 'dwd2xwsxw /dvw 'dwd figure 31: reset operation ))k w 567 :( $/( &/( 5( ,2[ 5% figure 30: automatic read at power on
rev. 0.2 / nov. 2005 44 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash :3 :( 9ff xv w 9 7+ figure 32: power on and data protection timing vth = 2.5 volt for 3.3 volt supply devices
rev. 0.2 / nov. 2005 45 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash 5sydoxhjxlghqfh 5splq9sduw zkhuh,/lvwkhvxpriwkhlqsxwfxuuqwvridooghylfhvwlhgwr wkh5%slq 5spd[lvghwhuplqhge\pd[lpxpshuplvvleoholplwriwu #9ff 97d ?&& / s) 9ff0d[9 2/ 0d[ 9 p$?, / , 2/ ?, / 5s lexv\ & / 5srkp lexv\ lexv\>$@ wuwi>v@ wi %xv\ 5hdg\ 9ff 92+ wu wi 92/ 9ff q p n n n n q p q p *1' 'hylfh rshqgudlqrxwsxw 5% figure 33: ready/busy pin electrical specifications
rev. 0.2 / nov. 2005 46 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash /rfn /rfn /rfn /rfnwljkw /rfn /rfn /rfnwljkw /rfnwljkw :3[ + /rfnwljkweorfnfrppdqg&k :3[ + 8qorfneorfn&rppdqgk6wduw%orfn$gguhvv &rppdqgk(qg%orfn$gguhvv :3[ + 8qorfneorfn&rppdqgk6wduw%orfn$gguhvv &rppdqgk(qg%orfn$gguhvv %orfn/rfnuhvhw :3[ /!qv :3[ + /rfneorfn&rppdqg$k :3[ + /rfnwljkweorfn&rppdqg&k %orfn/rfnuhvhw :3[ /!qv 3rzhu8s figure 34: lock/unlock fsm flow cart figure 35 : page prog ramming within a block m???g???gszig????g??gtzig???? kh{hgpugagk???goxp k???go][p k???g???????? w???g]z w???gzx w???gy w???gx w???gw o][p a ozyp a ozp oyp oxp l?upgy?????g????g???????gow??????????p kh{hgpugagk???goxp k???go][p k???g???????? w???g]z w???gzx w???gy w???gx w???gw o][p a oxp a ozp ozyp oxp
rev. 0.2 / nov. 2005 47 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash bad block management devices with bad blocks have the same quality level and th e same ac and dc characteristics as devices where all the blocks are valid. a bad block does not affect the performance of valid blocks because it is isolated from the bit line and common source line by a select transi stor. the devices are supplied with al l the locations inside valid blocks erased(ffh). the bad block information is wr itten prior to shipping . any block where the 1st byte in the spare area of the 1st or 2nd page(if the 1st page is bad) does not contain ffh is a bad block. the bad block information must be read before any erase is attempted as the bad block information may be erased. for the system to be able to recog- nize the bad blocks based on the original information it is recommended to crea te a bad block table following the flow- chart shown in figure 36. the 1st block, which is placed on 00h block address is guaranteed to be a valid block. bad replacement over the lifetime of the device additional bad blocks may deve lop. in this case the block has to be replaced by copying the data to a valid block. these additional bad blocks can be identified as attempts to program or erase them will give errors in the status register. as the failure of a page program operation does not affect th e data in other pages in the same block, the block can be replaced by re-programming the current data and copying th e rest of the replaced block to an available valid block. the copy back program command can be us ed to copy the data to a valid block. see the ?copy back program? section for more details. refer to table 21 for the recommended procedure to follow if an error occurs during an operation. operation recommended procedure erase block replacement program block replacement or ecc read ecc table 21: block failure <hv <hv 1r 1r 67$57 %orfn$gguhvv %orfn 'dwd ))k" /dvw eorfn" (1' ,qfuhphqw %orfn$gguhvv 8sgdwh %dg%orfnwdeoh figure 36: bad block management flowchart
rev. 0.2 / nov. 2005 48 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash write protect operation the erase and program operations are automatically reset when wp goes low (tww = 100ns, min). the operations are enabled and disabled as follows (figure 37~40) :: w k k :( ,2[ :3 5% k k w :: :( ,2[ :3 5% figure 37: enable programming figure 38: disable programming
rev. 0.2 / nov. 2005 49 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash k w 'k :: :( ,2[ :3 5% k w :: 'k :( ,2[ :3 5% figure 39: enable erasing figure 40: disable erasing
rev. 0.2 / nov. 2005 50 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash 5. appendix : extra features 5.1 automatic page0 read after power up the timing diagram related to this operation is shown in fig. 29 due to this functionality the cpu can dire ctly download the boot loader from the first page of the nand flash, storing it inside the internal cache and starting the execution after the download completed. 5.2 addressing for program operation within a block, the pages must be programmed consecutively from lsb (least significant bi t) page of the block to msb (most significant bit) page of the block. random address programming is prohibited. see fig. 34. 5.3 stacked devices access a small logic inside the devices allows th e possibility to stack up to 2 devices in a single package without changing the pinout of the memory. to do this the inte rnal address register can store up to 30 (1) addresses(512mbyte addressing field) and basing on the 2 msb pattern ea ch device inside the packag e can decide if remain active (1 over 4 ) or ?hang up? the connection entering the stand-by. note: 30 addresses are applied to hy27ug088g2m
rev. 0.2 / nov. 2005 51 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash table 22: 48-tsop1 - 48-lead plastic thin small outline, 12 x 20mm, package mechanical data symbol millimeters min typ max a 1.200 a1 0.050 0.150 a2 0.980 1.030 b 0.170 0.250 c 0.100 0.200 cp 0.100 d 11.910 12.000 12.120 e 19.900 20.000 20.100 e1 18.300 18.400 18.500 e 0.500 l 0.500 0.680 alpha 0 5 figure 41. 48-tsop1 - 48-lead plastic thin small outline, 12 x 20mm, package outline ' $ ',( $ h % / . ( ( & &3 $
rev. 0.2 / nov. 2005 52 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash symbol millimeters min typ max a 16.90 17.00 17.10 a1 13.00 a2 12.00 b 11.90 12.00 12.10 b1 10.00 b2 6.00 c1.00 c1 1.50 c2 2.00 d1.00 d1 1.00 e 0.55 0.60 0.65 cp1 0.65 0.70 0.75 cp2 0.95 1.00 1.05 % $ $ $ fs ( fs & & & % % '' 0 & $% 0 & $% table 23: 52-ulga, 12 x 17mm, package mechanical data figure 42. 52-ulga, 12 x 17mm, package outline (top view through package)
rev. 0.2 / nov. 2005 53 preliminary hy27ug088g(2/5/d)m series 8gbit (1gx8bit) nand flash marking information- tsop1/ulga packag marking example tsop1 / ulga k o r h y 2 7 x g x x 8 g x m x x x x y w w x x - hynix - kor - hy27xgxx8gxm xxxx hy: hynix 27: nand flash x: power supply g: classification xx: bit organization 8g: density x: mode m : version x: package type x: package material x: operating temperature x: bad block - y: year (ex: 5=year 2005, 06= year 2006) - ww: work week (ex: 12= work week 12) - xx: process code note - capital letter - sm all letter : hynix symbol : origin country : u(2.7v~3.6v) : single level cell+ double die+large block : 08(x8) : 8gbit : 2(1nce & 1r/nb; sequential row read disable) : 5(2nce & 1r/nb; sequential row read disable) : d(dual interface; sequential row read disable) : 1st generation : t(48-tsop1), u(52-ulga) : blank(normal), p(lead free) : c(0 ~70 ), e(-25 ~85 ) m(-30 ~85 ), i(-40 ~85 ) : b(included bad block), s(1~5 bad block), p(all good block) : fixed item : non-fixed item : part number

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